Semiconductor device, a method of manufacturing the same and storage media

ABSTRACT

Outside-cell wiring that extends the upper part of a macro cell to the direction of X axis is composed of the wiring layer of the upper layer than a terminal for a signal of the macro cell and this terminal is formed to extend in the direction of Y axis (direction that intersects the direction of X axis) so that the outside-cell wiring can be secured for a plurality of wiring channels. The macro cell and the outside-cell wiring are connected via this signal terminal.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device, a methodof manufacturing the semiconductor device and an art of storage media,and, more particularly, to an effective art that applies to a layoutdesign art of a semiconductor device.

BACKGROUND OF THE INVENTION

[0002] In the layout design of a semiconductor device, there are variouslayout design methods according to the type of the semiconductor device.A layout design method examined by the inventors is a macro cell (megacell) method, for example. This method is effective when a system, suchas a micro processor, a memory, an I/O (input/output) device and acustom circuit, is constructed as a single chip, for example. The methodis used to arrange various large and small circuit blocks in a chip areaand performs wiring between the circuit blocks.

SUMMARY OF THE INVENTION

[0003] However, in the art examined by the above inventors, theinventors have found out that the following problems are included.

[0004] That is, the wiring area required for connecting between circuitblocks results in a wasteful area on a semiconductor chip, and a chipsize increases. FIG. 20 shows an example of the general circumstances.In the drawing, a signal terminal 50 and a power supply terminal 51 arearranged on a cell frame of a circuit block 52. If a plurality ofcircuit blocks 52 are arranged in the horizontal direction (direction ofX axis) of FIG. 20, a wiring area 54 for arranging second layer wiring53 a and third layer wiring 53 b between the adjoining circuit blocks 52need be provided to connect signals between the circuit blocks 52. Thisincreases the chip size.

[0005] An object of the present invention is to provide an art that canreduce a chip size.

[0006] These and other objects, and new features of the presentinvention will become evident from a description and appended drawingsof this specification.

[0007] Among inventions disclosed in this application, an outline of therepresentative invention is briefly described below.

[0008] That is, in the present invention, a signal terminal for acircuit block is formed to secure a plurality of wiring channels in asecond direction that intersects a first direction where a plurality ofcircuit blocks are arranged, and the signal terminal is drawn out byusing first wiring that is the wiring of the upper layer than the signalterminal and extends to the first direction.

[0009] Further, in the present invention, the signal terminal is formedto extend in the second direction.

[0010] Moreover, in the present invention, the signal terminals arearranged in the first direction so that the signal terminals aremutually adjacent in the first direction, shifting them to the seconddirection.

[0011] Further, in the present invention, a power supply terminal isformed to extend in the second direction in the circuit block.

[0012] Moreover, in the present invention, a power supply terminal for acircuit block is formed to extend in a second direction that intersectsa first direction where a plurality of circuit blocks are arranged, andthe power supply terminal is drawn out by using first wiring that is thewiring of the upper layer than the power supply terminal and extends tothe first direction.

[0013] Further, in the present invention, a memory circuit is formed inthe circuit block.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a plan view of a macro cell that constructs asemiconductor device according to one embodiment of the presentinvention;

[0015]FIG. 2 is a plan view of a layout plane on which a wiring latticeand outside-cell wiring are added to FIG. 1;

[0016]FIG. 3 is an explanatory drawing of one example of the principalpart plane of the semiconductor device constructed by arranging themultiple macro cells of FIG. 1;

[0017]FIG. 4 is an explanatory drawing of another example of theprincipal part plane of the semiconductor device constructed byarranging the multiple macro cells of FIG. 1;

[0018]FIG. 5 is an explanatory drawing for describing the relationshipbetween the placement of the macro cell of FIG. 1 and lengthwisedimensions of a signal terminal;

[0019]FIG. 6 is a plan view of a macro cell that constructs asemiconductor device according to another embodiment of the presentinvention;

[0020]FIG. 7 is a plan view of a layout plane on which a wiring latticeand outside-cell wiring are added to FIG. 6;

[0021]FIG. 8 is an explanatory drawing of one example of the principalpart plane of the semiconductor device constructed by arranging themultiple macro cells of FIG. 1 and FIG. 6;

[0022]FIG. 9 is a plan view of an example of a macro cell according toanother embodiment of the present invention;

[0023]FIG. 10 is a plan view of a layout plane on which a wiring latticeis added to FIG. 9;

[0024]FIG. 11 is a principal part plan view showing the connected statebetween a power supply terminal, inside-cell wiring and outside-cellwiring of the macro cell of FIG. 9.

[0025]FIG. 12 is a sectional view of the line X1 to X1 of FIG. 9;

[0026]FIG. 13 is a plan view of an example of a semiconductor chip thatconstructs the semiconductor device that uses the macro cell of FIG. 9;

[0027]FIG. 14 is a plan view of the semiconductor chip before the wiringof FIG. 13 is arranged;

[0028]FIG. 15 is a plan view of an example of the macro cell accordingto further another embodiment of the present invention;

[0029]FIG. 16 is a principal part plan view of the semiconductor devicefor describing a wiring connection method when the macro cell of FIG. 15is used;

[0030]FIG. 17 is a principal part plan view of the semiconductor devicemanufactured by the wiring connection method described in FIG. 16;

[0031]FIG. 18 is an explanatory drawing of a computer used in amanufacturing method of the semiconductor device according to anotherembodiment of the present invention;

[0032]FIG. 19 is a flowchart when a semiconductor device is designedusing the computer of FIG. 18; and

[0033]FIG. 20 is an explanatory drawing of the layout design of thesemiconductor device examined by the inventors.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0034] Before the invention of this application is described in detail,the meanings of technical terms used in this application are describedbelow.

[0035] 1. A semiconductor device or semiconductor integrated circuitdevice includes not only a device that is produced on a semiconductor orinsulator substrate, such as a silicon wafer and a sapphire substrate,but also a device that is produced on other insulating substrates ofglass or the like, such as a TFT (thin-film-transistor) and STN(super-twisted-nematic) liquid crystal, unless otherwise specified inparticular.

[0036] 2. A macro cell indicates a circuit block or a function blockwhich has a higher function and larger scale than a basic cell. Themacro cell is classified into a hard macro in which a mask pattern isfixed and a soft macro in which library information is up to net listrepresentation and that generates the mask pattern every design. Themacro cell includes a standard cell (poly cell) of fixed height thatrepresents a small-scale logic gate, a module cell, such as a RAM(random access memory) that has a regular layout structure and isautomatically generated by a module generator in accordance with aninput parameter, a ROM (read only memory), a PLA (programmable logicarray), a multiplier, an adder or a data path, a CPU (central processingunit) or an analog cell and an I/O (input/output) cell. The macro cellregisters cell frame and terminal information for automatic placementand routing and simulation information, such as a function model, alogic model and a delay parameter, in a design system (computer or thelike) as a cell library in addition to the mask pattern information, andcan use them by simply calling them from the cell library in case ofsimulation. The RAM and ROM are memory circuits (memory modules). As anexample of the RAM, there is a DRAM (dynamic RAM), an SRAM (static RAM)or an FRAM (ferroelectric RAM). Further, as examples of the ROM, thereis a mask ROM (MROM) and a flash memory (EEPROM; electric erasableprogrammable ROM).

[0037] 3. Inside-cell wiring indicates signal and power supply wiringfor mainly constructing a desired circuit (function) within a cell.

[0038] 4. Outside-cell wiring (wiring outside a circuit block, firstwiring) indicates signal and power supply wiring for mainly connectingbetween a plurality of cells and constructing the entire circuit.

[0039] 5. An inner terminal indicates a terminal that is arranged in acell frame of a macro cell.

[0040] 6. An IP (intellectual property) indicates a circuit block inwhich an already designed circuit function block of which the operationis checked can be reused as a design asset.

[0041] 7. A net list indicates design data that represents a connectionrelationship of an integrated circuit or the like. The net list has aformat in which a computer can process data. In general, the connectionrelationship is hierarchically described to compact the data.

[0042] 8. A wiring lattice is a line which indicates a path (wiringchannel) through which wiring is placed and consists of a plurality ofwiring lattice lines that mutually cross at right angles. Besides, thereare two types of wiring lattices. In one type, the boundary between thewiring lattice and a macro cell matches, and in the other type, theboundary does not match. Since the former can place wiring in theboundary of the macro cell, wiring simplicity can be improved. Since thelatter can reduce a cell size, the size of a semiconductor chip can bereduced.

[0043] In the following embodiments, they are described by being dividedinto multiple sections or aspects when they are necessary forconvenience. Except when specified in particularly, the section andaspect are related mutually. One side is related to a part or all partsof modification examples, details and supplementary explanations of theother side.

[0044] Further, in the following embodiments, when reference is made tothe number of elements (including the number of items, numeric values,quantity and scope), the elements are not limited to the specific numberand can exceed or go below the specific number except when they arespecified in particular and are clearly limited to the specific numberon principle.

[0045] Moreover, in the following embodiments, needless to say, thecomponents (including element steps) are not necessarily indispensableexcept when they are specified in particular and considered to beindispensable clearly on principle.

[0046] Similarly, in the following embodiments, when reference is madeto shapes and position relationships of components, the componentssubstantially include those which are approximate or similar to theshapes except when they are specified clearly in particular andconsidered not to be indispensable on principle. This also applies tothe above numeric values and scope.

[0047] Further, in all drawings for describing this embodiment, the samesymbol are affixed to the same function and a description of therepetition is omitted.

[0048] Moreover, in this embodiment, an MIS-FET (metal insulatorsemiconductor field effect transistor) that stands for a field effecttransistor is abbreviated as an MIS, a p-channel type MIS-FET isabbreviated as a pMIS, and an n-channel type MIS-EFT is abbreviated asan nMIS.

[0049] The embodiments of the present invention are described below indetails with reference to the drawings.

[0050] (Embodiment 1)

[0051]FIG. 1 shows a plan view of a macro cell MC 1 that is a circuitblock that constructs a semiconductor device according to one embodimentof the present invention. Further, FIG. 2 shows a layout plan view onwhich a wiring lattice (dashed line) and outside-cell wiring L are addedto FIG. 1. Besides, the interval of mutually adjoining wiring latticeson the semiconductor device is about 0.5 μm, for example.

[0052] This micro cell MC 1 constructs a predetermined circuit functionby electrically connecting a plurality of integrated circuit elementsarranged in a cell frame, for example, using inside-cell wiring. Theinside-cell wiring is composed of first and second layer wiring. FIG. 1illustrates an input circuit A and an output circuit B of the macro cellMC1. The input circuit A consists of a CMIS (complementary MIS) invertercircuit and has a pMISQp land an nMISQn 1. Further, the output circuit Bhas a pMISQp 2 and an nMISQn 2. Besides, FIG. 2 illustrates a method bywhich the cell frame of the macro cell MC 1 is arranged on a wiringlattice line. The method of arranging the cell frame is not limited tothis method. For example, a method of arranging the cell frame by beingshifted by a half pitch between the adjoining wiring lattice lines canalso be used.

[0053] The macro cell MC 1 has a plurality of signal terminals Ts. Thisterminal Ts is a conductor unit for sending and receiving a signalbetween a circuit formed in the macro cell MC1 and a circuit outside themacro cell MC1 and formed using wiring on the top wiring layer in the MCcell MC 1. In the diagram, the terminal Ts is constructed using thesecond layer wiring, for example. Further, the diagram illustrates thestate in which the input of the input circuit A and the output of theoutput circuit B in the macro cell MC 1 are electrically connected. ThepMISQp 1 and nMISQn 1 gate electrodes of the input circuit A areelectrically connected to the terminal Ts and the pMISQp 2 and nMISQp 2source areas of the output circuit B are electrically connected to theterminal Ts. A power supply voltage Vdd is supplied to the pMISQp 1 andnMISQp 2 source areas and a power supply voltage Vss of lower potentialthan the power supply voltage Vdd is supplied to the nMISQn 1 and nMISQn2 source areas. Besides, these power supply voltages Vdd and Vss will bedescribed later. Further, the terminal Ts is electrically connected tothe input circuit A and the output circuit B using the second layerwiring, the first layer wiring that is the wiring layer of the lowerlayer than the second layer wiring or both the wiring.

[0054] Further, the terminal Ts, in the cell frame of the macro cell MC1, is arranged in the vicinity of a side that runs along the verticaldirection (direction of Y axis (second direction) and in a row along theside. Between the terminals Ts adjacent in the direction of Y axis, forexample, a space is placed so that the only one wiring lattice line thatextends to the horizontal direction (direction of X axis (firstdirection) of FIGS. 1 and 2 can be arranged. The area of the macro cellMC 1 can be reduced by arranging the terminal Ts in the cell frame inthis manner (that is, using an inner terminal). Further, the pluralterminals Ts can be arranged without increasing the area of the macrocell MC 1. However, the present invention is not limited to this. Forexample, it can also apply to the structure in which the terminal Ts isarranged on the cell frame. Moreover, the drawing illustrates the casewhere this terminal (inner terminal) Ts is arranged in a row, but canalso be arranged in a plurality of rows. This will be described later.

[0055] Further, in this embodiment, the terminal (inner terminal) Ts isformed along a wiring lattice line that extends to the direction of Yaxis and on the line, as shown in FIG. 2, using a plane and rectangularpattern that is long in the direction of Y axis. That is, the terminalTs extends to the direction of Y axis and is formed so that the pluralwiring lattice lines that extend to the direction of X axis can passthrough it. Hereupon, the direction of Y axis dimensions of the terminalTs are set here so that the terminal can pass through the two wiringlattice lines or more in the direction of X axis. The direct connectionfrom the outside of the macro cell MC1 to the terminal Ts is performedusing outside-cell wiring L that forms aerial wiring of the macro cellMC 1. This outside-cell wiring L consists of wiring of the wring layerof the upper layer than the terminal (inner terminal) Ts, for example,third layer wiring, and is arranged along a wiring lattice line thatextends to the direction of X axis and on the line. The outside-cellwiring L is electrically connected to the terminal Ts via a through holeTH (refer to FIG. 2). Besides, the through hole TH is mainly arranged inthe intersection between the wiring lattice line that extends to thedirection of X axis and the wiring lattice line that extends to thedirection of Y axis. The plural macro cells MC 1 can be arranged withoutany gap (even if a wiring area is not provided between the cells) byusing the structure of such macro cell MC 1. Further, as a result ofmaking the terminal Ts rectangular, the wiring channel efficiency in theplacement and routing process can be improved and degrees of freedom ofwiring can be improved. These can reduce a size (chip size) of asemiconductor chip.

[0056]FIGS. 3 and 4 show an example of a memory circuit (module), suchas a RAM or ROM, constructed by arranging m pieces of the macro cell MC1in the direction of X axis and n pieces of the macro cell MC 1 in thedirection of Y axis. FIG. 3 illustrates the case (address spaceextension) in which data input is made common and FIG. 4 illustrates thecase (bit width extension) in which an address is made common. Besides,in the symbols of FIGS. 3 and 4, LC is the outside-cell wiring for aclock signal, LA indicates the outside-cell wiring for an addresssignal, LDIN indicates the outside-cell wiring for a data input signaland LDOUT indicates the outside-cell wiring for a data output signal.Any one illustrates the outside-cell wiring L.

[0057] In FIGS. 3 and 4, the configuration of each macro cell MC 1 isidentical. For example, each macro cell MC 1 forms a RAM of apredetermined memory capacity. In FIG. 3, the macro cell MC 1 of whichthe data input is made common is arranged without any gap along theextending direction (direction of X axis) of the outside-cell wiring LC.Further, in FIG. 4, the macro cell MC 1 of which the address is madecommon is arranged without any space along the extending direction(direction of X axis) of the outside-cell wiring LA. The outside-cellwiring LA for the address signal, the outside-cell wiring LDIN for thedata input signal and the outside-cell wiring LDOUT for the data outputare arranged so as to extend the upper part of each macro cell MC to thedirection of X axis.

[0058] That is, as shown in FIG. 3, the outside-cell wiring LA for theaddress signal and the outside-cell wiring LDOUT for the data outputsignal are electrically connected to each different macro cell MC 1 andthe outside-cell wiring LDIN for the data input signal is electricallyconnected in common to these macro cells MC 1 respectively.

[0059] Further, as shown in FIG. 4, the outside-cell wiring LA of theaddress signal is electrically connected in common to these macro cellsMC1 respectively and the outside-cell wiring LDIN for the data inputsignal and the outside-cell wiring LDOUT for the data output signal areelectrically connected to each different macro cell MC 1.

[0060] According to this embodiment like this, as shown in FIGS. 3 and4, since the terminal Ts of each macro cell MC 1 can be drawn out usingthe outside-cell wiring L of the third wiring layer of the upper layer,a wiring area for arranging signal wiring need not be provided betweenthe macro cells MC 1. Accordingly, the plural macro cells MC 1 can bearranged without any gap in both the directions of X axis and Y axis.Therefore, a chip size can be reduced.

[0061] Further, in FIGS. 3 and 4, the outside-cell wiring LC for theclock signal is divided every macro cell MC 1. That is, the outside-cellwiring LC for the clock signal is electrically connected to eachdifferent macro cell MC 1. Accordingly, the power consumption of theentire semiconductor device can be reduced by operating only thenecessary macro cell MC 1. Further, a clock signal that differs everymacro cell MC can be input.

[0062]FIG. 5 is an explanatory drawing for describing the relationshipbetween the placement of the macro cell MC 1 and the lengthwisedimensions of the signal terminal Ts. The diagram illustrates the casewhere the lengthwise dimensions of the terminal Ts are set to dimensionsin which four wiring lattice lines that extend to the direction of Xaxis can be arranged. In this case, up to four macro cells MC 1 can bearranged without any gap in the direction of X axis. If this isexceeded, the outside-cell wiring cannot be arranged. Accordingly, inthat case, the case where the macro cell MC 1 is expanded to thedirection of Y axis is illustrated.

[0063] (Embodiment 2)

[0064] This embodiment describes an example in which a plurality ofcolumns of signal terminals are arranged. FIGS. 6 and 7 show the oneexample. FIG. 6 shows a plan view of a macro cell MC 2 that is a circuitblock that constructs a semiconductor device according to thisembodiment. Further, FIG. 7 shows a drawing in which a wiring lattice(dashed line) and out-wiring L are added to FIG. 6.

[0065] In the macro cell MC 2, the configuration other than theplacement of the terminal Ts is the same configuration described in themacro cell MC 1 of the embodiment 1. In this embodiment, a plurality ofcolumns of the terminal Ts are arranged in the direction of X axis.Further, the terminals Ts of mutually adjoining terminal columns arearranged, shifting them in the direction of Y axis. Accordingly, theefficient utilization of a wiring channel is enabled. For example, asshown in FIG. 7, the uppermost outside-cell wiring L1 (L) iselectrically connected via the uppermost terminal Ts1 (Ts) in theleftmost terminal column and the through hole TH. This outside-cellwiring L1 extends not only to the upper part of the terminal Ts1 butalso to the direction of X axis. Accordingly, if the position of theterminal Ts is not shifted to the direction of Y axis as describedabove, the connection unit (part of the wiring channel) of the terminalsTs2 a and Ta2 b in the second terminal column from the left is alsodamaged due to the placement of the uppermost outside-cell wiring L1. Inthis embodiment, since the position of the terminal Ts in the secondterminal column from the left is shifted to the direction of Y axisagainst the position of the terminal Ts in the uppermost terminalcolumn, the outside-cell wiring L1 can pass through the upper par of thewiring lattice line between terminals Ts2 a (Ts) and Ts2 b (Ts) that areadjacent to the direction of Y axis in the second terminal column fromthe left. Accordingly, in the second terminal column from the left, theconnecting part on the terminals Ts2 a and Ts2 b will not be damaged bythe outside-cell wiring L1. Thus, since the connectable part of theterminals Ts2 a and Ta2 b can be secured, the effective utilization ofthe wiring channel is enabled. Accordingly, since the degree of freedomof connecting the outside-cell wiring L can be secured, the reduction ofa chip size can be promoted.

[0066]FIG. 8 shows an example of a memory circuit (module), such as aRAM or ROM constructed by arranging the plural macro cells MC 1 and MC2. In the drawing, the configuration in which the sizes of the macrocells MC land MC 2 differ is illustrated. Further, in the drawing, thecase where the outside-cell wiring LC for the clock signals of theplural macro cells MC1 and MC2 of different sizes is made common isillustrated. Needless to say, multiple macro cells of which the sizesare identical but of which the types differ can be arranged.

[0067] (Embodiment 3)

[0068]FIG. 9 is a plan view of a macro cell MC 3 that constructs asemiconductor device according to another embodiment of the presentinvention. FIG. 10 is a layout plan view on which a wiring lattice(dashed line) is added to FIG. 9. FIG. 11 is a principal part enlargedplan view of the macro cell MC 3 that is the circuit block of FIG. 9 andFIG. 12 shows a sectional view of the line X1 to X1 of FIG. 9respectively.

[0069] The macro cell MC 3 forms a memory circuit (module), such as theRAM or ROM. A memory cell array MA, an X decoder area XDA, a Y decoderarea YDA and an input/output circuit area I/OA are arranged in the cellframe of the macro cell MC 3. The memory cell array MA forms a memorycircuit, such as a DRAM, an SRAM or an FRAM. That is, the memory cellarray MA forms a memory cell, a word line and a data line. An X decodercircuit is formed on the X decoder area XDA and a Y decoder circuit isformed on the Y decoder area YDA. The memory cell is arranged in theintersection between the word line and data line. The word line iselectrically connected to the X decoder circuit and the data line iselectrically connected to the Y decoder circuit. An input/outputbidirectional circuit is arranged in the input/output circuit area I/OAin addition to the input circuit and output circuit.

[0070] The placement of the signal terminal Ts is the same placement asdescribed in the embodiment 2. Hereupon, the terminal (inner terminal)Ts is arranged in the input/output circuit area I/OA. That is, a wiringdelay can be reduced by arranging the terminal Ts (inner terminal) inthe input/output circuit area I/OA. Further, for this embodiment, in theinput/output circuit area I/OA within the cell frame of the macro cellMC 3, power supply terminals Tvdd and Tvss are arranged at the positionadjacent to a group of the signal terminals Ts. The power supplyterminals Tvdd and Tvss supply a power supply voltage to the macro cellMC 3 and are formed along the lengthwise direction (direction of Y axis)of the signal terminal using strip patterns that extend from the upperend to the lower end of the cell frame. Accordingly, the power of themacro cell MC 3 can be obtained from any site within the dimensions ofthe direction of Y axis. Consequently, degrees of freedom of leading theoutside-cell wiring for a power supply around can be improved. Further,since the power supply can be obtained at an effective site or number asmuch as possible according to the macro cell MC 3, the stability ofpower supply potential can be improved. The power supply terminal Tvddsupplies a relatively high potential power supply voltage Vdd, and, forexample, is set to about 1.8 V to 3.3 V. Moreover, the power supplyterminal Tvss supplies reference potential (relatively low potentialpower supply voltage Vss) of a semiconductor device, and, for example,is set to about 0 V.

[0071]FIG. 11 shows the connected states between these power supplyterminals Tvdd and Tvss and between power supply inside-cell wiringLIvdd 1 and LIvss 1 and power supply outside-cell wiring Lvdd and Lvss.The power supply terminals Tvdd and Tvss consist of the second layerwiring, for example. These terminals Tvdd and Tvss are electricallyconnected to the power supply inside-cell wiring LIvdd 1 and LIvss 1comprised of the first layer wiring respectively via a though hole TH1.Further, these terminals Tvdd and Tvss are electrically connected to thepower supply outside-cell wiring Lvdd and Lvss composed of the thirdlayer wiring respectively via a through hole TH 2. Further, someoutside-cell wiring L composed of the third layer wiring simply passthrough the upper part of these power supply terminals Tvdd and Tvss.Further, the power supply terminals Tvdd and Tvss are arranged on awiring lattice line that extends to the direction of Y axis.

[0072] Thus, the power supply outside-cell wiring Lvdd and Lvss thatextend the upper part of the macro cell MC 3 and its outside to thedirection of X axis are composed of the wiring layer of the upper layerthan the power supply terminals Yvdd and Tvss and are electricallyconnected to the power supply outside-cell wiring LIvdd and LIvss of thelower layer than the power supply terminals Tvdd and Tvss via the powersupply terminals Tvdd and Tvss. By forming the power supply terminalsTvdd and Tvss using strip patterns that extend from the upper end to thelower end of the cell frame of the macro cell MC 3, degrees of freedomof the connection between the power supply outside-cell wiring Lvdd andLvss can be improved and degrees of freedom of the placement of thesignal outside-cell wiring that extends the upper part of the macro cellMC 3 can be improved. That is, this can improve and highly integrate theplacement density of the power supply outside-cell wiring Lvdd and Lvssthat pass through the upper part of the macro cell MC 3 and the signaloutside-cell wiring. Further, degrees of freedom of the connectionbetween the power supply terminals Tvdd and Tvss and the power supplyinside-cell wiring LIvdd and LIvss composed of the first layer wiringcan be improved. Besides, the first layer wiring LIvdd and LIvss areelectrically connected to an integrated circuit element that constructseach circuit of the macro cell MC 3, for example.

[0073] Subsequently, the longitudinal structure of a part of the macrocell MC 3 is described using FIG. 12. Besides, FIG. 12 illustrates asectional cross of nMISQn 2 for the output circuit as an integratedcircuit element. However, the integrated circuit element is not limitedto this. For example, there are various integrated circuit elements,such as pMISs, diodes, bipolar transistors, resistors or capacitors.

[0074] A semiconductor substrate (hereinafter simply referred to as asubstrate) iS that constructs a semiconductor chip consists of p typesingle crystal silicon, for example. For example, a trench-typeisolation unit 2 (trench isolation) is formed in the isolation area onthe principal surface of the substrate 1S. The isolation unit 2 isformed by burying an insulating film, such as oxide silicon (SiO₂), in atrench dug at a predetermined depth from the principal surface of thesubstrate 1S. The isolation unit 2 is not limited to a trench-type onebut can be changed into various types. For example, it can also beaccepted as a field insulating film consisting of oxide silicon or thelike formed by the LOCOS (local oxidization of silicon) method.

[0075] Further, in the active region enclosed by this isolation unit 2,semiconductor areas called a p well PWL 1, PWL 2 and an n well NWL 1 Iare formed over a predetermined width from the principal surface (devicesurface) of the substrate 1S. Among them, the p well PWL 2 is enclosedby a semiconductor area called an n type buried area NISO. That is, thep well PWL 2 is electrically isolated from the substrate 1S. This cansuppress or prevent noises from propagating to the p well PWL 2 via thesubstrate 1S. Further, the potential of the p well PWL 2 can be set tothe potential that differs from that of the substrate 1S.

[0076] For example, impurities that form a p type area, such as boron(B), are introduced into the p wells PWL 1 and PWL 2 and impurities thatform an n type area, such as phosphor (P) or arsenic (As), areintroduced into the n well NWL 1 and the n type buried well NISO.Hereupon, nMISQn 2 is formed on the p well PWL 2. The NMISQn 2 has apair of semiconductor areas 3 for a source and a drain, a gateinsulating film 4 and a gate electrode 5A. This nMISQn 2 channel, in thesubstrate 1S between the pair of semiconductor areas 3, for example, isformed in the interface part between the gate insulating film 4 belowthe gate electrode 5A and the substrate 1S (surface channel).

[0077] For example, phosphor or arsenic are introduced into thesemiconductor area 3 for the nMISQn 2 source and drain and the area isset as an n type area. The gate insulating film4 consists of an oxidesilicon film, for example. Further, the gate insulating film 4 can alsouse an acid nitride film. This can improve hot carrier resistance. Thegate electrode 5A consists of n type low resistance polysilicon, forexample. For example, phosphor or arsenic is introduced into this gateelectrode 5A. This gate electrode 5A is not limited to a single film oflow resistance polysilicon and can be changed into various types. Forexample, what is called a polycide gate structure in which cobaltsilicide (CoSi_(x)) is formed on an n type low resistance polysiliconfilm can also be used. Titan silicide (TiSi_(x)) and tungsten silicide(Wsi_(x)) can also be employed instead of this cobalt silicide, but thiscobalt silicide can reduce resistance more easily. Further, what iscalled a polymetal gate structure in which a tungsten (W) film is piledup on the n type low resistance polysilicon film via a barrier film,such as nitride titan (WN), can also be used. In this case, theresistance of the gate electrode 5A and the contact resistance betweenthe gate electrode 5A and wiring can greatly be reduced.

[0078] For example, interlayer insulating films 6 a and 6 b consistingof oxide silicon are sequentially piled up on the principal surface ofthis substrate 1S from the lower layer. The first wiring layer is formedon the interlayer insulating film 6 a and the second wiring layer isformed on the interlayer insulating film 6 b. The signal terminal Ts andthe power supply terminals Tvdd and Tvss are formed on the interlayerinsulating film 6 b. These terminal Ts, Tvdd and Tvss consist ofaluminum (Al) or an aluminum-Si-copper alloy, for example, and areformed as patterns when the same patterning is made.

[0079] The terminal Ts is electrically connected to inside-cell wiringLIs 1 composed of the first layer wiring via the through hole THperforated in the interlayer insulating film 6 b. The inside-cell wiringLIs1 is electrically connected to the one-sided semiconductor area 3 ofthe nMISQn 2 via a contact hole CNT 1 perforated in the interlayerinsulating film 6 a. Besides, the inside-cell wiring LIs 1 consists ofthe same material as the terminal Ts.

[0080] The terminal Tvss is electrically connected to inside-cell wiringLIvss 1 composed of the first layer wiring via the through hole TH 1perforated in the interlayer insulating film 6 b. The inside-cell wiringLIvss 1 is electrically connected to a p⁺ type semiconductor area 7 ofthe p well PWL 1 via a contact hole CNT 2 perforated in the interlayerinsulating film 6 a. Besides, the inside-cell wiring LIvss 1 consists ofthe same material as the inside-cell wiring LIs 1 and is formed aspatterns when the same patterning as the inside-cell wiring LIs 1 ismade.

[0081] Subsequently, a plan view of a semiconductor chip (hereinaftersimply referred to as a chip) created using the technical idea of thisembodiment like this is shown in FIGS. 13 and 14. Besides, FIG. 14 showsa plan view of a chip 1C before wiring processing is performed when amacro cell is arranged.

[0082] The chip 1C consists of a fragment of the plane and squaresubstrate 1S and, for example, a computer system is formed (Soc; SystemOn Chip) in this chip 1C. However, the present invention itself islimited to the SoC and can apply to various systems.

[0083] A plurality of external terminals 8 are arranged in theperipheral vicinity of the chip 1C along their external periphery.Needless to say, the placement of the external terminal 8 is not limitedto this, and, for example, the external terminal 8 can also be arrangedin the center of the chip 1C. The peripheral area of the chip 1Cincluding the placement area of this external terminal 8 is used as theinput/output circuit area of the chip 1C, that is, the area in which anI/O cell is arranged. Besides, in general, the external terminal 8 iselectrically connected to a lead of a package via a bonding wire and abump electrode (protruded electrode) connected in the state where theydirectly touch it, and is electrically connected to an external device(or external circuit) outside the chip 1C via the wiring on a wiringsubstrate on which the package is mounted.

[0084] A plurality of macro cells MC 3, MC 4 and MC 5 are arranged inthe internal circuit area of the chip 1C. The macro cell MC 3 on which aRAM is formed as described above is arranged without generating any gapbetween mutual adjoining macro cells. Further, for example, a ROM isformed on the macro cell MC 4. This macro cell MC 4 is also arrangedwithout generating any gap between mutual adjoining macro cells.Accordingly, since a wasteful area can be reduced or eliminated, a chipsize can be reduced. The power supply terminals Tvdd and Tvss of themacro cell MC 3 adjacent to the direction of Y axis are mutuallyelectrically connected. Further, the power supply terminals Tvdd andTvss of the macro cell MC 4 adjacent to the direction of Y axis aremutually electrically connected.

[0085] The area excluding the placement area of these macro cells MC3and MC4 is a core cell area or a custom area. For example, a desiredlogic circuit is formed on the macro cell MC 5 arranged in this corecell area or custom area. The technical idea of the present invention isalso incorporated in this macro cell MC 5. Between the respectiveadjoining macro cells MC 3 to MC 5, a wiring area for connecting thesemacro cells is prepared. Outside-cell wiring for electrically connectingthe respective macro cells MC 3 to MC 5 is arranged in this wiring area.The structure of inside-cell wiring and outside-cell wiring is the samestructure as described previously. In the case of placement design, asshown in FIG. 14, after the plural macro cells MC 3 to MC 5 arearranged, a semiconductor device having a desired circuit function isdesigned on the whole by arranging the outside-cell wiring that connectsthese macro cells MC 3 to MC 5.

[0086] (Embodiment 4)

[0087] An example of a macro cell MC 6 that is a circuit block in thesemiconductor device of this embodiment is shown in FIG. 15. In thismacro cell MC 6, the signal terminal Ts is plane and square, and awiring channel area C for connecting the signal terminal Ts andoutside-cell wiring is arranged around (in the direction of Y axis inparticular) of the signal terminal Ts. This wiring channel area C itselfis a virtual area provided on data for the placement and routing in thedesign stage of the semiconductor device. Whether wiring is arranged inthis wiring channel area C or not is determined according to theconnected state with the outside-cell wiring.

[0088] According to this embodiment like this, since a signal terminalTs can be shortened, the wiring capacitance by this terminal Ts can bereduced in comparison with the embodiments 1 to 3. In particularly, whena wiring signal rate is strict, an effect is produced in the reductionof a wiring delay by applying this technical idea. Such structure ofthis embodiment and the structure of the embodiments 1 to 3 may also berealized in the same macro cell. For example, particularly, at a sitewhere a critical path is arranged, the signal terminal is made plane andsquare as described in this embodiment. At other sites, the signalterminal Ts can be made plane and rectangular as described in theembodiments 1 to 3. This enables both the reduction of a chip size andthe improvement of a characteristic (signal speed). Further, a terminalcolumn can variably be changed, for example, the first column of theterminal column is changed as described in the embodiment 1 and thesecond column of the terminal column can be changed as described in thisembodiment or vice versa. In this case, not only the same effect as theembodiment 2 can be obtained, but also the characteristic (signal speed)can be improved.

[0089]FIG. 16 shows an example of the connection method between theoutside-cell wiring LC and LA and the signal terminal Ts when the pluralmacro cells MC 6 are arranged. Hereupon, in the macro cells MC 6 of thesecond column or later, the outside-cell wiring LC and LA are onceconnected to the inside-cell wiring LIs 2 in the wiring channel area viathe through hole TH and are electrically connected to the terminal Tsvia the inside-cell wiring LIs 2.

[0090] A principal part plan view of such structured semiconductordevice is shown in FIG. 17. In the macro cell MC 6 of the first column,the signal terminal Ts uses a usually plane and square terminal. Theoutside-cell wiring LC and LA are electrically connected directly to theterminal Ts of the first column via the through hole TH. In the macrocells MC 6 of the second column or later, the outside-cell wiring LC andLA are electrically connected to the inside-cell wiring LIs 2 that isthe second layer wiring via the through hole TH. This inside-cell wiringLIs 2 extends to the direction of Y axis of FIG. 17 and is connected tothe terminal Ts. That is, the outside-cell wiring LC and LA areelectrically connected to the terminal Ts formed in one body with theinside-cell wiring LIs 2 via it. In the macro cell MC 6 of the thirdcolumn, the dimensions in the direction of Y axis of the inside-cellwiring LIs 2 are longer than the inside-cell wiring LIs 2 of the macrocell MC 6 of the second column. If the same length is specified, this isbecause the outside-cell wiring LC and LA and the terminal Ts of themacro cell MC 6 of the third column cannot be connected. In thisexample, a chip size can be reduced. Further, since wiring capacitancecan be reduced, characteristics (signal speeds) can be improved.

[0091] (Embodiment 5)

[0092] The macro cell MC 1, MC 2, MC 3 or MC 6 (hereinafter referred toas a macro cell MC) that is the circuit block described in theembodiments 1 to 4 can be used as an IP component that constructs a partof integrated circuits. The data for specifying this macro cell(hereinafter referred to as IP module data) is stored in a storagemedium, such as a magnetic disk, a floppy disk, a hard disk, a CD-ROM,an MO (magneto-optical disk) in the state in which it can be read on thecomputer.

[0093] This IP module data is used to design an integrated circuit to beformed on one chip 1C using a computer. The IP module data has graphicpattern data that defines graphic patterns to be formed on the chip 1Cand function data that defines a macro cell function.

[0094] The graphic pattern data is used to form a mask pattern used, forexample, when a semiconductor device is manufactured, for example,drawing data used to form the mask pattern. The mask pattern datadefines a graphic pattern every circuit formation layer, such as asemiconductor area (active region), element isolation area, gateelectrode, wiring layer, insulating film and connection hole (contacthole and a through hole) on the chip 1C and can generate a photomaskpattern in the lithography technique. Further, the function data is usedto describe the macro cell function using a computer language, such as aHDL (hardware description language).

[0095]FIG. 18 shows an example of a computer 10, such as an engineeringworkstation, a personal computer or a design apparatus used in thedesign of an integrated circuit. This computer 10 connects typicallyshown peripheral equipment, such as a display 10 b, a keyboard 10 c anda disk drive 10 d, to a processor board on which a processor and amemory are mounted and a main body 10 a in which various interfaceboards are installed. The graphic pattern data and the IP module dataincluding the function data are stored in the storage medium 11.Although not limited in particular, the IP module data stored in thestorage medium 11 is read in the main body 10 a of the computer 10 bymounting the storage medium 11 on the disk drive 10 d. For example, whenthe read IP module data is the description data described using the HDL,the computer 10 decodes this and performs processing. To decode the dataand perform the processing, the computer 10 executes a specific program.The computer 10 may also be a distributed processing system. Forexample, each of disk access, layout operation and a human-machineinterface is processed using an individual computer and the processingresult may also be used in cooperation. Besides, if the capacity of IPmodule data increases and cannot be stored in the single storage medium11, the IP module data ought also be stored over the plural storagemedia 11. Needless to say, the IP module data is divided so as topreviously be stored in the plural storage media 11 and ought also bestored in the plural storage media 11.

[0096] The design processing that employs a macro cell MC can bepositioned as the processing included in a part of the processing thatdesigns a semiconductor device, such as a microcomputer in which the IPmodule data is read from the storage medium 11 to the computer 10 andthe macro cell MC that corresponds to the read IP module data isincluded as a built-in module.

[0097]FIG. 19 entirely shows an example of the processing that designs asemiconductor device using the IP module data. The method of designprocessing can be regarded as a manufacturing method of thesemiconductor device, since the semiconductor device is manufacturedusing a mask pattern formed by this method.

[0098] First, in logic composition, processing, such as connectionbetween macro cells, is performed (process 100). Hereupon, logiccircuits (a logic diagram and a net list) are automatically generatedfrom high level design data (a hardware description language, a logicalexpression and a truth table). In the logic composition process untilthe final net list is generated, for example, logic is optimized byrepeating scanning, such as logic minimization), factoring andflattening.

[0099] In a subsequent logic check, logic composition is checkedlogically (process 101). Hereupon, whether a logic circuit operates ornot as a designer intends is checked. For example, a net list is inputtogether with logical operations and rise/fall time of each logic gateand test vectors (a series of input signal patterns for testing a logiccircuit function) are applied. Subsequently, logic check is performed byacquiring the output signal knowledge as an expected value and comparingit with the expected value.

[0100] After this logic check, the layout design of the entireintegrated circuit is performed (process 102). Hereupon, in accordancewith logical design, a mask pattern layout that becomes a subject copyof a photo mask is created. Integrated circuit elements, such astransistors and resistors, are arranged determining their dimensions soas to satisfy the specification function based on a logic circuit (netlist) of a semiconductor device and wiring is performed between theseintegrated circuit elements. Hereupon, the design rule from the processside must also be followed. Placement and routing are optimizedconsidering electrical properties and a chip size is reduced as much aspossible.

[0101] The invention made by these inventors is specifically describedbased on the embodiments above. The present invention is not limited tothe embodiment, and, needless to say, can variously be changed so longas it will not deviate from the purpose.

[0102] For example, in the embodiments 1 and 2, the case where thesignal terminals in a macro cell are plane and rectangular, but they arenot restricted to this case. For example, a macro cell structure inwhich a plane and rectangular terminal and a usually plane and squareterminal are arranged ought also be used. This plane and square terminalcan use a signal terminal common to a plurality of macro cells, forexample. This can reduce an occupied area of this entire terminal group.

[0103] Further, what is called the damascene wiring structure in whichwiring is performed by providing a drench or a hole in an interlayerinsulating film and burying a conductor film (for example, Cu wiring) init may also be employed instead of the wiring structure of theembodiments 1 to 5.

[0104] In the above description, the case where the invention mainlymade by the inventors applies to SoC that is the field of utilization asthe background is described, but the invention is not limited to it. Forexample, the invention can also be applied to another semiconductordevice, such as an ASIC (application specific IC) that stands for a gatearray and a standard cell.

[0105] Among the inventions disclosed according to this application, theeffect obtained by the representative invention is simply describedbelow.

[0106] That is, according to the present invention, a signal terminal ofa circuit block can be secured for a plurality of wiring channels in asecond direction that intersects a first direction in which a pluralityof circuit blocks are arranged and the signal terminal is drawn outusing first wiring that is the wiring of the upper layer than the signalterminal and extends to the first direction. Accordingly, since thecircuit block that is adjacent to the first direction can be arrangedwithout any gap, a chip size can be reduced.

What is claimed is:
 1. A semiconductor device comprising a plurality ofsignal terminals of a circuit block, wherein the signal terminals arearranged along a direction that intersects an extending direction of awiring which is a wiring of an upper layer and outside the circuit blockconnected to the signal terminals, and wherein each of the signalterminals is arranged in the direction that intersects the extendingdirection outside the circuit block so that spaces for a plurality ofwiring channels can be secured.
 2. The semiconductor device according toclaim 1, wherein a plurality of the circuit blocks are arranged alongthe extending direction of the wiring outside the circuit blocks and thesignal terminals of each of the circuit blocks and the wiring outsidethe circuit blocks are electrically connected to each other.
 3. Thesemiconductor device according to claim 2, wherein a wiring area isprovided between a group of different circuit blocks among the circuitblocks.
 4. The semiconductor device according to claim 1, wherein thesignal terminal is extended in the direction that intersects theextending direction of the wiring outside the circuit block.
 5. Thesemiconductor device according to claim 1, wherein the plurality of thesignal terminals are arranged along the extending direction of theoutside-cell wiring and the position of the terminals for mutuallyadjoining signals along the extending direction of the outside-cellwiring are shifted to the direction that intersects the extendingdirection of the outside-cell wiring.
 6. The semiconductor deviceaccording to claim 1, wherein the signal terminal is arranged in a frameof the circuit block.
 7. The semiconductor device according to claim 1,wherein the signal terminal is constituted of a top wiring layer in thecircuit block.
 8. The semiconductor device according to claim 1, whereina power supply terminal that extends to the direction that intersectsthe extending direction of the wiring outside the circuit block isprovided in the frame of the circuit block.
 9. The semiconductor deviceaccording to claim 8, the power supply terminal is constituted of a topwiring layer in the circuit block.
 10. A semiconductor device, wherein apower supply terminal of a circuit block is extended to the directionthat intersects the extending direction of power supply wiring that iswiring of the upper layer and is connected to the power supply terminal,then extends the upper part of the circuit block.
 11. The semiconductordevice according to claim 10, wherein the power supply terminal isextended from end to end in the frame of the circuit block.
 12. Thesemiconductor device according to claim 10, wherein the power supplyterminal is constituted of the top wiring layer in the circuit block.13. A semiconductor device, comprising: a plurality of circuit blocksarranged along a first direction; and a first wiring that extends to thefirst direction and electrically connects between the plurality ofcircuit blocks, wherein a plurality of signal terminals are arranged ineach of the plurality of circuit blocks along a second direction thatintersects the first direction; wherein each of the plurality of signalterminals secures spaces for a plurality of wiring channels in thesecond direction; and wherein the first wiring arranged on the wiringlayer of the upper layer is electrically connected to each of theplurality of signal terminals.
 14. The semiconductor device according toclaim 13, each of the plurality of signal terminals is extended to thesecond direction.
 15. The semiconductor device according to claim 13,wherein a plurality of each of the plurality of signal terminals arearranged along the first direction and the signal terminals that aremutually adjacent to the first direction are arranged, shifting theposition to the second direction.
 16. The semiconductor device accordingto claim 13, wherein each of the plurality of signal terminals isarranged in the frame of the circuit block.
 17. The semiconductor deviceaccording to claim 13, wherein each of the plurality of signal terminalsis constituted of the top wiring layer in the circuit block.
 18. Thesemiconductor device according to claim 13, wherein a power supplyterminal that extends to the second direction is provided in the frameof the circuit block.
 19. The semiconductor device according to claim18, wherein the power supply terminal is constituted of the top wiringlayer in the circuit block.
 20. The semiconductor device according toclaim 13, wherein the circuit block is a memory circuit, the firstwiring constructs a wiring for an address signal, and the first wiringis connected in common to the circuit block.
 21. The semiconductordevice according to claim 13, wherein the circuit block is a memorycircuit, the first wiring is wiring for data input, and the first wiringis connected in common to the circuit block.
 22. The semiconductordevice according to claim 13, wherein the circuit block is connected towiring for a different clock signal.
 23. The semiconductor deviceaccording to claim 1, wherein the circuit block is a memory circuit andthe signal terminal is formed on an input/output circuit area of thememory circuit.
 24. A manufacturing method of a semiconductor device,comprising the steps of: (a) arranging a plurality of circuit blocksalong a first direction; and (b) electrically connecting between theplurality of circuit blocks using first wiring that extends to the firstdirection, wherein a plurality of signal terminals are arranged in eachof the plurality of circuit blocks along a second direction thatintersects the first direction; wherein spaces for a plurality of wiringchannels are secured in the second direction in each of the plurality ofsignal terminals; and wherein the first wiring is arranged on the wiringlayer of the upper layer than the signal terminal and electricallyconnected to the signal terminal.
 25. A storage medium that stores datafor designing an integrated circuit to be formed on a semiconductorchip, wherein the data stored in the storage medium has data of aplurality of circuit blocks arranged along a first direction and firstwiring data that extends to the first direction and electricallyconnects between the plurality of circuit blocks; wherein each of theplurality of circuit blocks has data of a plurality of signal terminalsarranged along a second direction that intersects the first direction;wherein each of the plurality of signal terminals has data in whichspaces for a plurality of wiring channels are secured in the seconddirection; and wherein data in the connected state between each of theplurality of signal terminals and the first wiring arranged on thewiring layer of the upper layer is provided.
 26. The storage mediumaccording to claim 25, comprising data arranged in the state in whicheach of the plurality of signal terminals is extended in the seconddirection.
 27. The storage medium according to claim 25, comprising datain which each of the plurality of signal terminals is arranged along thefirst direction and the signal terminals that are mutually adjacent tothe first direction are arranged, shifting the position to the seconddirection.
 28. The storage medium according to claim 25, comprising datain which each of the plurality of signal terminals is arranged in theframe of the circuit block.
 29. The storage medium according to claim25, wherein a semiconductor integrated circuit is designed using thestorage medium.
 30. The semiconductor device according to claim 14,wherein the circuit block is a memory circuit, and wherein the signalterminal is formed on the input/output circuit area of the memorycircuit.
 31. The semiconductor device according to claim 30, wherein thefirst wiring is a wiring for an address signal or a wiring for data. 32.The semiconductor device according to claim 24, wherein the circuitblock is a memory circuit, and wherein the signal terminal is formed onthe input/output circuit area of the memory circuit.
 33. A semiconductordevice, comprising: a plurality of memory circuits arranged along afirst direction; and a plurality of first wiring that are electricallyconnected to the plurality of memory circuits, wherein a signal terminalis arranged in each of the plurality of memory circuits; wherein theplurality of first wiring are formed on the wiring layer of the upperlayer of the signal terminal, and extend over the terminal for thesignal along the first direction; wherein each of the signal terminalssecures spaces for a plurality of wiring channels in a second directionthat intersects the first direction; and wherein each of the pluralityof first wiring is arranged on a different wiring channel in theplurality of wiring channels and is electrically connected to theterminal for the different signal in the signal terminals of theplurality of memory circuits arranged in the first direction.
 34. Thesemiconductor device according to claim 33, comprising: a second wiringformed on the same layer wiring layer as the first wiring, wherein thesecond wiring is electrically connected to each of the signal terminalsof the plurality of memory circuits positioned on the same wiringchannel.
 35. The semiconductor device according to claim 33, wherein thefirst wiring is a wiring for an address signal.
 36. The semiconductordevice according to claim 33, wherein the first wiring is a wiring fordata.
 37. The semiconductor device according to claim 33, wherein thefirst wiring is a wring for a clock signal.
 38. The semiconductor deviceaccording to claim 33, wherein the signal terminal is formed on aninput/output circuit area of the memory circuit.
 39. The semiconductordevice according to claim 34, wherein the first wiring is one of wiringsfor the address signal and for the data; and wherein the second wiringis the other of wirings for the address signal and for the data.
 40. Thesemiconductor device according to claim 33, wherein in each of thememory circuit, a plurality of the signal terminals are arranged in thefirst direction and second direction, and the signal terminals adjacentto the first direction are arranged, shifting the position to the seconddirection.